/**
  ******************************************************************************
  * @author     Chris
  * @since      2024/7/1 14:14
  *
  * @file       hd_nrf24l01.h
  * @brief      Header file of Xxx hardware driver.
  *
  * @note       This file contains the Xxx object declaration.
  *
  * @warning    None.
  ******************************************************************************
  * Change Logs:
  *   Date          Author       Notes
  *   2024/7/1     Chris        the first version
  *
  ******************************************************************************
  */


#ifndef JLC_SKY_NRF24L01_H
#define JLC_SKY_NRF24L01_H

#include "stm32f407xx.h"
#include "pd_gpio.h"
#include "pd_spi.h"

struct NRF24L01 {
     SPI *spi;

     GPIO *csn;   // Chip select, low level enable
     GPIO *ce;    // Chip Enable, set chip work mode
     GPIO *irq;   // Interrupt signal,

    /**
     * ---------------------------
     * | 2   | 4   | 6    | 8    |
     * | VCC | CSN | MOSI | IRQ  |
     * ---------------------------
     * | 1   | 3   | 5    | 7    |
     * | GND | CE  | SCK  | MISO |
     * ---------------------------
     * @param this
     */
    void (*init)(struct NRF24L01 *this);

    uint8_t (*check)(struct NRF24L01 *this);
};

extern const struct NRF24L01Class {
    struct NRF24L01 (*new)(  SPI *spi,   GPIO *csn,   GPIO *ce,   GPIO *irq);
} NRF24L01;

/**
 * NRF24L01 command macro define
 */
#define READ_REG_CMD    0x00   // Define read command to register
#define WRITE_REG_CMD   0x20   // Define write command to register
#define RD_RX_PLOAD     0x61   // Define RX payload register address
#define WR_TX_PLOAD     0xA0   // Define TX payload register address
#define FLUSH_TX        0xE1   // Define flush TX register command
#define FLUSH_RX        0xE2   // Define flush RX register command
#define REUSE_TX_PL     0xE3   // Define reuse TX payload register command
#define NOP             0xFF   // Define No Operation, might be used to read status register

/**
 * NRF24L01 register address macro define
 */
#define CONFIG          0x00    // 'Config' register address
#define EN_AA           0x01    // 'Enable Auto Acknowledgment' register address
#define EN_RXADDR       0x02    // 'Enabled RX addresses' register address
#define SETUP_AW        0x03    // 'Setup address width' register address
#define SETUP_RETR      0x04    // 'Setup Auto. Retrans' register address
#define RF_CH           0x05    // 'RF channel' register address
#define RF_SETUP        0x06    // 'RF setup' register address
#define STATUS          0x07    // 'Status' register address
#define OBSERVE_TX      0x08    // 'Observe TX' register address
#define CD              0x09    // 'Carrier Detect' register address
#define RX_ADDR_P0      0x0A    // 'RX address pipe0' register address
#define RX_ADDR_P1      0x0B    // 'RX address pipe1' register address
#define RX_ADDR_P2      0x0C    // 'RX address pipe2' register address
#define RX_ADDR_P3      0x0D    // 'RX address pipe3' register address
#define RX_ADDR_P4      0x0E    // 'RX address pipe4' register address
#define RX_ADDR_P5      0x0F    // 'RX address pipe5' register address
#define TX_ADDR         0x10    // 'TX address' register address
#define RX_PW_P0        0x11    // 'RX payload width, pipe0' register address
#define RX_PW_P1        0x12    // 'RX payload width, pipe1' register address
#define RX_PW_P2        0x13    // 'RX payload width, pipe2' register address
#define RX_PW_P3        0x14    // 'RX payload width, pipe3' register address
#define RX_PW_P4        0x15    // 'RX payload width, pipe4' register address
#define RX_PW_P5        0x16    // 'RX payload width, pipe5' register address
#define FIFO_STATUS     0x17    // 'FIFO Status Register' register address


#define TX_ADR_WIDTH       5
#define RX_ADR_WIDTH       5
#define TX_PLOAD_WIDTH    32
#define RX_PLOAD_WIDTH    32

#define MAX_TX  		0x10
#define TX_OK   		0x20
#define RX_OK   		0x40


#endif //JLC_SKY_NRF24L01_H
